Spi Transfer Modes. Or if you prefer you can combine spicpol clock polarity idle high iff this is set or spicpha clock phase sample on trailing edge iff this is set flags. The simplest configuration of spi is a single master single slave system but one master can control more than one slave more on this below.
Polarity and clock phase. Sclk clock line for the clock signal. Pass a pointer to a byte which will return rd or assign wr the spi transfer mode.
Spi has following four lines miso mosi ss and clk miso master in slave out the slave line for sending data to the master.
You would therefore have to either move the nrf21540 to other pins or you could use the same pins and reinitialize the spi bus between each time you need to switch modes. The spi interface defines no protocol for data exchange limiting overhead and allowing for high speed data streaming. Dual spi is another variation of spi that came before quad spi which as the name implies uses 2 data lines to transfer data instead of 4 as in quad spi. Each spi clock transfers data in full duplex mode.